Initial version with 4K flash sequence memory, 64 bytes RAM, 32 sequences
sequence 0 runs on reset
V1.2
29 January 1999
6K flash sequence memory, 96 bytes RAM
new sequence instructions
CMPWC, compare working register with constant
CMPWM, compare working register with memory
BITWC, test working register with mask constant
ADCWC, add constant and carry to working register
ADCWM, add memory and carry to working register
SBCWC, subtract constant and carry from working register
SBCWM, subtract constant and carry from working register
BITA, test bit output port A, bit 0-7
BITB, test bit output port B, bit 0-3
BITC, test bit output port C, bit 0-7
LDWI, load working register indirect
STWI, store working register indirect
ROLWC, rotate working register left through carry
RORWC, rotate working register right through carry
RLCWC, rotate working register left circular
RRCWC, rotate working register right circular
BRA, relative branch
BEQ, branch when the zero flag is 1
BNE,branch when the zero flag is 0
BCS, branch when the carry flag is 1
BCC, branch when the carry flag is 0
SHLM, shift memory left 1 bit, 0 in bit0, bit7 in carry
SHRM, shift memory right 1 bit, 0 in bit0, bit0 in carry
ROLM, rotate memory left 1 bit, carry in bit0, bit7 in carry
RORM rotate memory right 1 bit, carry in bit7, bit0 in carry
DECM, decrement memory
INCM, increment memory
ENASQ, Enable sequence
DISSQ, disable sequence
RHAS, return here asynchronously (seq28-31)
RHOI, return here on interval (seq28-31)
CALL, call sequence (seq3-27)
Sequence functions
sequence 1 runs on start Node command
sequence 2 runs on stop Node command
sequence 28 - 31 can work with RHOI (return here on 1ms interval time)
or RHAS (return here asynchronously)
this function can be used for time consuming sequences,
main functions and other sequences working normal.
V2.0
20 December 1999
Sequences can be assembled into native code: execution speed up to eight
times faster then version 1.2; code size will be 1.5 up to 3 times larger
16k Flash sequence memory
160 bytes extra local user memory (no access via CAN bus), now 256 bytes
in total.
LDWM/STWM instruction can access only the 256 byte RAM (no I/O)
LDWM/STWM instruction now affects the Z flag
SYNC instruction now can disable the automatically generated SYNC pulse
(after a CAN message)
Sequence #3 and/or #4 can be an interrupt routine for very fast CAN
message response (application layer conditions have to be met).
new sequence instructions
OUTAC, output constant value to parallel output port A
OUTBC, output constant value to parallel output port B
BCANE, program branch when operating system can send a CAN message
BCANF, program branch when operating system cannot send a CAN message
LDWIO, load working register from I/O location (replacement for LDWM
with an operand of 96-127)
STWIO, store working register into I/O location (replacement for STWM
with an operand of 96-127)
TESTM, test memory location
CLRM, clear memory location
SHOC, shift-out constant value via the SPI shifter
BIT0M - BIT7M, test bit in memory
I2OC, shift-out constant value via the I2C bus
RSOM, shift-out memory location via RS232 interface
RSIM, shift-in memory location from RS232 interface
RSCFC, configure RS232
RSOC, shift-out constant value via RS232 interface
I2SPD, select standard or high speed I2C interface
CANSND, trigger immediate can message transmission if application layer
conditions are met
FSTINT, temporarily disable or re-enable the fast interrupt processing
of sequence #3 and #4
new sequencer I/O memory locations
RSCFG, configure RS232
RSOUT, shift-out via RS232 interface
RSIN, shift-in from RS232 interface
RSRBL, get amount of received characters in RS232 buffer
RSTBF, get amount of free characters in RS232 buffer
V2.1
7 December 2000
64 bytes of EEPROM memory added
processing of tables with constants from program memory added
generating of tables is handled by sequence assembler
new sequencer instruction
LDWE, read EEPROM memory location direct into W
STWE, write W direct into EEPROM memory location
LDWEI, read EEPROM memory location indirect into W
STWEI, write W indirect into EEPROM memory location
SWAPWM, exchange contents of W with memory location
TABLE, set table pointer
LDWT, load working register from table, direct index
LDWTI, load working register from table, indirect index