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Last Modified: 7 January 2000

6172 CAN Core Module

Sequencer versions

Sequencer version 1.2 

The CAN Core module can be configured to process sequences of instructions to interface between the CAN bus and miscellaneous I/O chips (parallel or serial via SPI or I2C), or it can run an application, executing commands from the CAN bus and sending back replies.

A sequence can be started on an action on the CAN bus, an action in the custom I/O or on time intervals.

Generating the sequencer code and tables is made easy using the free available Sequencer Assembler V1.2

More information about working with the sequencer can be found in 'How it works' and the Application Notes

The sequence memory consists of 6 Kb flash memory, the user must write the sequence program and configuration into this memory.

96 bytes of RAM memory is available for data exchange, writing to a particular memory location can start a preselected sequence, reading from a RAM memory location can start a preselected sequence, when the sequence is finished the data will be available for transmission.

Sequencer data memory

The data memory contains 96 user RAM bytes, the (memory mapped) sequencer I/O and I/O configuration.

The I/O locations (112 - 127) are primarily intended to be able to control all sequencer I/O directly from the CAN bus (without any sequence), for debug and test procedures.

Sequencer data memory

Memory address

Symbolic name

Description

Access Type

0

-

user memory

read / write

up to

95

96 - 111

-

reserved for future use

-

112 (low byte)

113 (high byte)

PWMFL

PWMFH

Frequency output configuration (PWM)

read / write

Data

Description

2 .. 65535

output frequency is (7.5E6 / data) Hz

Output is updated only after writing memory location PWMDH, to prevent change when PWMDx still contains an 'old' value

114 (low byte)

115 (high byte)

PWMDL

PWMDH

Duty cycle output configuration (PWM)

read / write

Data

Description

up to value in PWMDx

output is high for 100 * (PWMDx / PWMFx) percent of the time (always high if this value is equal or higher then PWMDx, always low if this value is zero)

Output is updated only after writing memory location PWMDH.
After writing PWMDH, the user should wait at least a complete PWM cycle (up to 9 milli-seconds if PWMFx is at maximum) before writing a new PWM value.

116

MISC

Miscellaneous command:

write only

Data

Description

0

outputs a stop condition on the I2C bus

1

outputs a start condition on the I2C bus

2

indicates that the next I2C bus read command is the last before STOP

3

activates the SYNC output for 2 micro-seconds

4

clears the READY output

5

sets the READY output

117

I2OUT

I2C shift-out, write starts shift out after write

write only

118

I2IN

I2C shift-in, read starts shift-in before read

read only

119

SPISPD

Shift speed configuration (SPI shifter)

read / write

Data

Description

0

0.3 µS / bit

1

1.1 µS / bit

2

4.3 µS / bit

3

17.1 µS / bit

120

 

SPIPAT

 

Shift pattern configuration (SPI shifter)

read / write

Data

Description

0

1

2

3

4

5

6

7

Input data is shifted in at the centre point of the drawn data bits

121

SPIOUT

Shift-out register, write starts shift out after write

write only

122

SPIIN

Shift-in register, read starts shift-in before read

read only

123

PORTA

Parallel output port A, Out1 - Out8

read / write

124

PORTB

Parallel output port B, Out9 - Out12

read / write

125

PORTC

Parallel input port C, In1 - In8

read only

126

AIN1

Read 8 bits analogue input 1

read only

127

AIN2

Read 8 bits analogue input 2

read only

Reading a write only location returns a zero.
Writing a read only location has no effect.  
Sequencer program memory

The 6 Kb flash memory contains the sequencer programs and information about how to start them.

Sequence program memory

Description

0000h - 001Fh

Identification string (defined by user)

0020h

Sequencer version number (12 for version 1.2)

0021h - 003Fh

table of interval times

0040h - 007Fh

table of sequence start addresses

0080h - 00DFh

table of sequences start on write
(start after data memory write)

00E0h - 013Fh

table of sequences start on read
(start before data memory read)

0140h - 17FFh

sequence command memory
 
Sequence intervals

A sequence will start automatically after the selected interval time.

Sequence intervals (0021h - 003Fh)

Sequence

address

Interval in 10 ms

1,2

0021h, 0022h

invalid

3

0023h

0, 1 - 255

up to

up to

0, 1 - 255

31

003Fh

0, 1 - 255

no sequence starts when interval = 0 

Sequence start addresses

The following table defines the start addresses for each sequence.

Sequence start addresses (0040h - 007Fh)

Sequence

address

Start address

0

0040h

0xxxh

1

0042h

0xxxh

up to

up to

0xxxh

31

007Eh

0xxxh

no sequence starts when start address = 0000h

Sequence 0 starts automatically after power up or Node reset (hardware or reset node command),
Sequence 1 starts automatically after a start node command,
Sequence 2 starts automatically after a stop node command.

Sequences 0,1 and 2 cannot be started on an interval or reading/writing of user memory or a CALL command. 

Sequence start on write

By writing a memory location by the application, e.g. a CANopen PDO write, a sequence can be started.
The sequence will be started after write to the memory location.

Sequence start on write (0080h - 00DFh)

User memory

address

Sequence

0

0080h

3 - 31

1

0081h

3 - 31

up to

up to

3 - 31

95

00DFh

3 - 31

no sequence starts when sequence = 0 

Sequence start on read

By reading memory location by the application, e.g. a CANopen PDO write, a sequence can be started.
The sequence will be started before a read from a memory location.

Sequence start on read (00E0h - 013Fh)

User memory

address

Sequence

0

00E0h

3 - 31

1

00E1h

3 - 31

up to

up to

3 - 31

95

013Fh

3 - 31

no sequence starts when sequence = 0

Starting a sequence by reading or writing memory is only valid via CAN bus accesses (e.g. SDO, PDO). Any internal access from within a sequencer program will not start another sequence. 

Sequence command memory

Sequencer command memory (0140h - 17FFh)

address

command

0140h

first command

0142h

2nd command

up to

more commands

17FEh

last possible command

A command always contains 2 bytes, the first byte (at even address) is the command, the 2nd byte contains additional data.

When writing the command table to memory, the 6 Kb FLASH memory is in fact completely erased first. So the user must send the complete table.
It is not necessary to send the complete 6 Kb, only the first 140h bytes are mandatory, the rest depends on the total sequencer program length.

Sequencer instructions
 

Symbolic Name

Code

Data

Description

Execution time in µS (Note)

Valid Flags

Working register

LDWM

00h

0 - 95

Load working register from user memory

5.5

- -

112

Load working register from PWM frequency low

8.7

- -

113

Load working register from PWM frequency high

8.7

- -

114

Load working register from PWM duty cycle low

8.7

- -

115

Load working register from PWM duty cycle high

8.7

- -

118

Load working register from I2C bus (shift in a byte)

99.1

- -

119

Load working register from SPI shift speed configuration

8.6

- -

120

Load working register from SPI shift pattern configuration

9.2

- -

121

Load working register with last in-shifted byte (during last shift in or last shift out....)

9.2

- -

122

Load working register from SPI bus (shift in a byte)

-

- -

Shift_Speed (memory location 71) = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3

10.4 - 11.2
16.4 - 17.5
42.4 - 47.9
145.1 - 163.2

- -

123

Load working register from parallel output port A (latch)

9.6

- -

124

Load working register from parallel output port B (latch)

9.6

- -

125

Load working register from parallel input port C

12.9

- -

126

Load working register from 8 bits analogue input 1

25.3 - 26.9

- -

127

Load working register from 8 bits analogue input 2

STWM

01h

0 - 95

Store working register to user memory

5.5

- -

112

Store working register to PWM frequency low

8.7

- -

113

Store working register to PWM frequency high

8.7

- -

114

Store working register to PWM duty cycle low

8.7

- -

115

Store working register to PWM duty cycle high

18.0 - 22.4

- -

116

Storing to MISC makes no sense because special sequencer instructions exist to do this (I2STP, I2STA, I2STP, SYNC, CRDY, SRDY)

-

- -

MISC = 0
MISC = 1
MISC = 2
MISC = 3
MISC = 4
MISC = 5

20.4
30.5
10.4
13.0
11.5
12.0

- -

117

Store working register to I2C bus (shift out a byte)

98.7

- -

119

Store working register to SPI shift speed configuration

12.4

- -

120

Store working register to SPI shift pattern configuration

12.4

- -

121

Store working register to SPI bus (shift out a byte)

-

- -

Shift_Speed (memory location 71 = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3

10.4 - 11.2
16.4 - 17.5
42.4 - 47.9
145.1 - 163.2

123

Store working register to parallel output port A

10.8

- -

124

Store working register to parallel output port B

11.1

- -

LDWC

02h

0 - 255

Load working register with constant (immediate value, 0 - 255)

4.1

- -

ANDWC

03h

0 - 255

Bit wise logical AND working register with constant

5.1

Z -

ORWC

04h

0 - 255

Bit wise logical OR working register with constant

5.1

Z -

XORWC

05h

0 - 255

Bit wise logical XOR working register with constant

5.1

Z -

SHLWC

06h

n

Shift working register n bits left (n = 1 - 7), empty places filled with 0

4.3 + n*0.93

Z C

SHRWC

07h

n

Shift working register n bits right (n = 1 - 7), empty places filled with 0

4.3 + n*0.93

Z C

ADDWC

08h

0 - 255

Add constant to working register

5.1

Z C

SUBWC

09h

0 - 255

Subtract constant from working register

5.2

Z C

ANDWM

0Ah

0 - 95

Bit wise logical AND working register with memory

5.8

Z -

ORWM

0Bh

0 - 95

Bit wise logical OR working register with memory

5.8

Z -

XORWM

0Ch

0 - 95

Bit wise logical XOR working register with memory

5.8

Z -

ADDWM

0Dh

0 - 95

Add memory to working register

5.8

Z C

SUBWM

0Eh

0 - 95

Subtract memory from working register

5.8

Z C

Output port A

OUTA

10h

0 - 95

Output user memory location to parallel output port A

7.0

- -

SETA

11h

0 - 7

Set bit in parallel output port A, bit number 0 - 7

5.6

- -

RESA

12h

0 - 7

Reset bit in parallel output port A

5.7

- -

TGLA

13h

0 - 7

Toggle bit in parallel output port A

5.6

- -

MASKA

14h

0 - 255

Set port A masking (the bits allowed to change, NOTE)

4.1

- -

BITA

15h

0 - 7

Test bit in parallel output port A, bit number 0 - 7 (bit always reads as zero if MASKA is zero for that bit)

5.7

Z -

Working Register

CMPWC

18h

0 - 255

Compare working register with constant

5.1

Z C

CMPWM

19h

0 - 95

Compare working register with memory location

5.4

Z C

BITWC

1Ah

0 - 7

Test bit in working register, bit number 0 - 7

5.4

Z -

ADCWC

1Ch

0 - 255

Add constant and Carry to working register

5.6

Z C

ADCWM

1Dh

0 - 95

Add memory and Carry to working register

6.3

Z C

SBCWC

1Eh

0 - 255

Subtract constant and Carry from working register

6.4

Z C

SBCWM

1Fh

0 - 95

Subtract constant and Carry from working register

6.3

Z C

Output port B

OUTB

20h

0 - 95

Output user memory location to parallel output port B

7.2

- -

SETB

21h

0 - 3

Set bit in parallel output port B

5.6

- -

RESB

22h

0 - 3

Reset bit in parallel output port B

5.7

- -

TGLB

23h

0 - 3

Toggle bit in parallel output port B

5.6

- -

MASKB

24h

0 - 15

Set port B masking (the bits allowed to change, NOTE)

4.1

- -

BITB

25h

0 - 3

Test bit in parallel output port B, bit number 0 - 3 (bit always reads as zero if MASKB is zero for that bit)

5.7

Z -

Working Register

LDWI

28h

0 - 95

Load working register indirect (memory location contains effective memory location)

5.8

- -

STWI

29h

0 - 95

Store working register indirect

5.8

- -

ROLWC

2Ah

n

Rotate working register n bits left (n = 1 - 7), through Carry

4.8 + n*0.93

Z C

RORWC

2Bh

n

Rotate working register n bits right (n = 1 - 7), through Carry

4.8 + n*0.93

Z C

RLCWC

2Ch

n

Rotate working register n bits left (n = 1 - 7), circular

4.7 + n*1.07

Z C

RRCWC

2Dh

n

Rotate working register n bits right (n = 1 - 7), circular

4.7 + n*1.07

Z C

NOTE: when the contents of the indirect memory location is higher then 95, the LDWI or STWI command doesn't do anything.

Input port C

INPC

30h

0 - 95

Input parallel input port C to user memory location

9.0

- -

SEQCE 

31h

dd

Activate a sequence on a port C (0 - 3 = in1 - in4) input edge

8.4

- -

Bit

Description

0 - 1

port bit number (0 - 3)

2

sets rising (1) or falling (0) edge

3 - 7

selects the sequence to start (1 - 31), no sequence when 0

SEQCL

32h

dd

Activate a sequence on a port C (4 - 7 = in5 - in8) input level

6.3

- -

Bit

Description

0 - 1

port bit number (0 - 3 = bit 4 - 7)

2

sets high level (1) or low (0) level

3 - 7

selects the sequence to start (1 - 31), no sequence when 0

MASKC

34h

0 - 255

Set port C masking (the bits allowed to read, NOTE)

4.1

- -

BITC

35h

0 - 7

Test bit in parallel input port C, bit number 0 - 7 (bit always reads as zero if MASKC is zero for that bit)

9.5

Z -

Branch

BRA

40h

rel

Program branch : rel = -128 .... 127
1 - 128 instructions backward
0 - 127 instructions forward

5.2

- -

BEQ

41h

rel

Program branch when the zero flag is one

4.4
(no branch)

5.9
(branch)

- -

BNE

42h

rel

Program branch when the zero flag is zero

- -

BCS (BLO)

43h

rel

Program branch when the carry flag is one

- -

BCC (BHS)

44h

rel

Program branch when the carry flag is zero

- -

Memory

SHLM

48h

0 - 95

Shift memory location left one bit, shift a zero into bit 0, bit 7 into Carry

5.2

Z C

SHRM

49h

0 - 95

Shift memory location right one bit, shift a zero into bit 7, bit 0 into Carry

5.2

Z C

ROLM

4Ah

0 - 95

Rotate memory location left one bit, shift Carry into bit 0, bit 7 into Carry

5.8

Z C

RORM

4Bh

0 - 95

Rotate memory location right one bit, shift Carry into bit 7, bit 0 into Carry

5.8

Z C

DECM

4Ch

0 - 95

Decrement memory location

5.2

Z -

INCM

4Dh

0 - 95

Increment memory location

5.2

Z -

Serial bus

SHOM

50h

0 - 95

Shift-out user memory location via the SPI shifter

-

- -

Shift_Speed (memory location 71) = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3

10.0 - 10.8
16.0 - 17.5
42.0 - 47.5
144.7 - 162.8

SHIM

51h

0 - 95

Shift-in user memory location via the SPI shifter

-

- -

Shift_Speed (memory location 71) = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3

10.4 - 11.2
16.4 - 17.9
42.4 - 47.9
145.1 - 163.2

SHSPD

52h

0 - 3

Set SPI shifter shift speed (data is same as memory location 71)

8.7

- -

SHPAT

53h

0 - 7

Set SPI shifter shift pattern (data is same as memory location 72)

8.7

- -

I2C bus

I2OM

60h

0 - 95

Shift-out user memory location via the I2C bus

95.3

- -

I2IM

61h

0 - 95

Shift-in a byte from the I2C bus to the user memory location

96.5

- -

I2STP

62h

0

Output a STOP condition on the I2C bus

16.1

- -

I2STA

63h

0

Output a START condition on the I2C bus

25.7

- -

I2LST

64h

0

Indicates that the next read command will be the last, and should not be acknowledged

4.3

- -

Miscellaneous

DELAY

70h

n

Delay, n times 2 us

3.8 + n * 2

- -

SYNC

71h

0

Outputs a 2 uS high pulse on the SYNC output

6.3

- -

CRDY

72h

0

Clears READY output (low, out1 .. out12 are tri-stated)

4.3

- -

SRDY

73h

0

Sets READY output (high, out1 .. out12 are activated)

4.3

- -

CALL

74h

3 - 27

Subroutine call of another sequence, even if it is disabled.
Sequences 0-2 and 28-31 should not be called.

11.2

- -

ERROR

75h

1 - 8

Notify an error to the application layer (like CANopen)

5.2

- -

ERROF

76h

1 - 8

Notify end of error to the application layer

5.2

- -

ENASQ

7Bh

0,1-31

Enable execution of all (data = 0) sequences or given sequence (data = 1 - 31)

7.1 (all)
8.4 (one)

- -

DISSQ

7Ch

0,1-31

Disable execution of all (data = 0) sequences or given sequence (data = 1 - 31)

7.0 (all)
8.4 (one)

- -

RHAS

7Dh

28 - 31

Return here Asynchronously
Suspend processing of current sequence, allow 6172 to perform its internal tasks (even start another sequence) and continue processing as soon as possible.
The I/O masks and the working register are saved.

The data must reflect the sequence number containing the RHAS command.

9.5

- -

RHOI

7Eh

28 - 31

Return here on interval:
Suspend processing of current sequence, allow 6172 to perform its internal tasks (even start another sequence) and continue processing synchronized by 1 milli-second timer.
The I/O masks and the working register are saved.

The data must reflect the sequence number containing the RHOI command.

9.0

- -

ENDSQ

7Fh

0

End of sequence

4.3

- -

NOTE on execution times:

These are the minimum execution times; the 6172 has three internal interrupt routines (1 mS timer, CAN bus and RS232). These interrupts stay enabled while executing a sequence, so the execution time of a sequence command can be longer then stated. 

Notes on MASK commands

The MASKx command allows the user to define the port bits used/affected by the sequence.

This is a simple way to prevent a lot of code if a sequence just uses some bits of a output port, while the other bits should be unaffected.

If a bit is one in the MASKx operand, the user can output to and read from this bit. When a operand bit is zero, writing to this bit has no effect on the output ports, reading it always reads zero.

At the beginning of a sequence started on read/write or timer, the masks of all three ports are set to one's. A sequence started with the CALL command does not set the masks (uses the caller's mask). 

IMPORTANT NOTE

The 6172 contains a internal watchdog which resets the CAN MCM if it is not serviced within 50 milli-seconds. This watchdog is cleared at the start of a sequence and after the end of it. Be shure that a sequence (including CALLed sequences) does not take more then 50 milli-seconds, or the system will reset.

During the execution of a sequence the CAN bus is not serviced by the main program (received messages are placed in a buffer), so it is bad practice to create a sequence that takes 50 milli-seconds anyway.

If for some reason (like a unintended recursive CALLed sequence) the watchdog does intervene, the restart of the sequencer will keep on resulting in a watchdog reset. In this case it may be impossible to write a new (correct) sequence in memory (because the SDO's aren't serviced).

By holding the IRQ input (connector J4, pin 14) low for 0.5 seconds after the RST input (connector J4, pin 15) is pulsed low and high again, the sequencer will be inhibited until the next (soft- or hardware) reset (with IRQ high). This enables theuser to write a new (correct) sequence into memory.

Example Sequence

write data into the AD7840 D/A converter.
Shift input is connected to the serial output ,
CS is connected to bit 1 of port A
14 data bits on address 22 and 23

Example sequence

Symbolic name

Code

Data

Description

SHSPD

52h

1

Shift speed: 1.1 us per bit

SHPAT

53h

2

Shift pattern

RESA

12h

1

Output port A: reset bit 1, CS of AD7840 low

SHOM

50h

23

Shift-out memory byte: 23, (high byte)

SHOM

50h

22

Shift-out memory byte: 23, (low byte)

SETA

11h

1

Output port A: set bit 1, CS of AD 7840 high

ENDSQ

7Fh

0

End of sequence
 
Generating the sequencer code and tables is made easy using the free available Sequencer Assembler

Information about the differences between Sequencer versions.

More information about working with the sequencer can be found in 'How it works' and the Application Notes