Home

Last Modified: 21 March 2001

6172 CAN Core Module
Sequencer version 1.0  Sequencer version 1.2  Sequencer version 2.0 Sequencer versions.

Sequencer version 2.1

The CAN Core module can be configured to process sequences of instructions to interface between the CAN bus and miscellaneous I/O chips (parallel or serial via SPI or I2C), or it can run an application, executing commands from the CAN bus and sending back replies.

A sequence can be started on an action on the CAN bus, an action in the custom I/O or on time intervals.

The sequencer can run up to 32 sequence programs created by the free available Sequencer Assembler V2.1 

This assembler can generate the code for 'emulated' mode or generate native code for the CAN Core module's CPU (this code executes much faster but uses more program memory).

More information about working with the sequencer can be found in 'How it works' and the Application Notes

The sequence memory consists of 16 Kb flash memory, the user must write the sequence program and configuration into this memory.

96 bytes of RAM memory is available for data exchange, writing to a particular memory location can start a preselected sequence, reading from a RAM memory location can start a preselected sequence, when the sequence is finished the data will be available for transmission.

Additional 160 bytes of RAM are available for internal sequencer use (256 bytes total RAM).

64 bytes of EEPROM memory are available for non-volatile storage.

Sequencer data memory

The data memory contains 256 user RAM bytes, the sequencer I/O and I/O configuration.

The I/O locations (107 - 127) are primairily intended to be able to control all sequencer I/O directly from the CAN bus (without any sequence), for debug and test procedures.

Sequencer data memory, accessable via CAN bus

Memory address

Symbolic name

Description

Access Type

 Dis

0

-

user memory, accessable via CAN bus

This memory is cleared after power on, and by a reset command via the CAN bus

read / write

  

up to

95

96 - 106

-

reserved for future use

-

  

107

RSCFG

Configure RS232, zero means RS232 usable as in 6390

write only

X

Bit

Description

0 - 3

RS232 databit / stopbit / parity combination
0001 = 7data / 2stop / no
0010 = 8data / 1stop / no
0011 = 8data / 2stop / no
0100 = 7data / 1stop / odd
0101 = 7data / 2stop / odd
0110 = 8data / 1stop / odd
0111 = 7data / 1stop / even
1000 = 7data / 2stop / even
1001 = 8data / 1stop / even

4 - 6

RS232 BAUDrate specification
000: 300 BAUD
001: 600 BAUD
010: 1200 BAUD
011: 2400 BAUD
100: 4800 BAUD
101: 9600 BAUD
110: 19200 BAUD
111: 38400 BAUD

7

0: hardware (CTS/RTS) handshake
1: software (XON/XOFF) handshake

108

RSOUT

Shift-out memory location via RS232 interface

write only

 X

109

RSIN

Shift-in memory location from RS232 interface

read only

 X

110

RSRBL

Get amount of received characters in RS232 buffer

read only

 X

111

RSTBF

Get amount of free characters in RS232 buffer

read only

 X

112 (low byte)

113 (high byte)

PWMFL

PWMFH

Frequency output configuration (PWM)

read / write

 X

Data

Description

2 .. 65535

output frequency is (7.5E6 / data) Hz

Output is updated only after writing memory location PWMDH, to prevent change when PWMDx still contains an 'old' value

114 (low byte)

115 (high byte)

PWMDL

PWMDH

Duty cycle output configuration (PWM)

read / write

 X

Data

Description

up to value in PWMDx

output is high for 100 * (PWMDx / PWMFx) percent of the time (always high if this value is equal or higher then PWMDx, always low if this value is zero)

Output is updated only after writing memory location PWMDH.
After writing PWMDH, the user should wait at least a complete PWM cycle (up to 9 milli-seconds if PWMFx is at maximum) before writing a new PWM value.

116

MISC

Miscellaneous command:

write only

 X

Data

Description

0

outputs a stop condition on the I2C bus

1

outputs a start condition on the I2C bus

2

indicates that the next I2C bus read command is the last before STOP

3

activates the SYNC output for 2 micro-seconds

4

clears the READY output

5

sets the READY output

6

 sets standard (100 kbps) I2C speed

7

 sets fast (330 kbps) I2C speed

117

I2OUT

I2C shift-out, write starts shift out after write

write only

 X

118

I2IN

I2C shift-in, read starts shift-in before read

read only

 X

119

SPISPD

Shift speed configuration (SPI shifter)

read / write

 X

Data

Description

0

0.3 µS / bit

 Shift instructions will wait for end of transfer

1

1.1 µS / bit

2

4.3 µS / bit

3

17.1 µS / bit

120

 

SPIPAT

 

Shift pattern configuration (SPI shifter)

read / write

 X

Data

Description

0

1

2

3

4

5

6

7

Input data is shifted in at the centre point of the drawn data bits

121

SPIOUT

Shift-out register, write starts shift out after write.
When reading this location the byte that was shifted in during the last shift-out is read.

read / write

  

122

SPIIN

Shift-in register, read starts shift-in before read

read only

  

123

PORTA

Parallel output port A, Out1 - Out8

read / write

  

124

PORTB

Parallel output port B, Out9 - Out12

read / write

 X

125

PORTC

Parallel input port C, In1 - In8

read only

 X

126

AIN1

Read 8 bits analogue input 1

read only

 X

127

AIN2

Read 8 bits analogue input 2

read only

 X
Sequencer data memory, accessable via sequencer commands

0 - 95

-

 Also accessable via CAN bus, cleared after reset

read / write

  

96 - 255

-

NOT accessable via CAN bus

This memory is cleared after power on, but NOT cleared by a reset command via the CAN bus

Reading a write only location returns a zero.
Writing a read only location has no effect.

IMPORTANT NOTE:

Accessing the I/O locations (96 - 127) must be done using the LDWIO or STWIO commands, memory is accessed by LDWM/STWM and all other memory referencing commands.

THE I/O LOCATION CANNOT BE ACCESSED USING LDWM/STWM.

A sequence written for older versions (< 2.0) of the sequencer must be modified.

Sequencer program memory

The 16 Kb flash memory contains the sequencer programs and information about how to start them.

Sequence program memory

Description

1000h - 101Fh

Identification string (defined by user)

1020h

Sequencer version number (20 for version 2.0)
1021h 0: indicates an emulated sequence
1: indicates a native code sequence

1022h

reserved
1023h - 103Fh table of interval times, sequence 3-31

1040h - 107Fh

table of sequence start addresses

1080h - 10DFh

table of sequences start on write (start after data memory write)

10E0h - 113Fh

table of sequences start on read (start before data memory read)

1140h - 4FFFh

sequence command memory
 
Sequencer EEPROM memory

The 64 byte EEPROM memory can contain user/application configuration data.

EEPROM memory

Description

00h - 3Fh

 EEPROM data memory
 

EEPROM is accessed using 4 special sequencer command.
Erasing / programming of an EEPROM taken care of in background by the 6172 firmware.

An EEPROM write command (STWE or STWEI command) stores the EEPROM data into an internal buffer, so the sequencer will continue to run while EEPROM is being programmed in background. When the EEPROM write buffer is full, the STWE or STWEI instruction will wait for at most 22 milli-second.

When the EEPROM is read (LDWE or LDWEI commands), the sequencer can wait up to 11 milli-seconds when the background task is erasing or programming a byte (even if there was no EEPROM write command given, because the 6172 firmware also uses the EEPROM).

When multiple EEPROM read or write commands are given, use sequence #28..#31 to do this, otherwise watchdog problems may arise (a sequence may not take more then 50 milli-seconds execution time without the use of the RHAS or RHOI commands).

Accessing EEPROM is prohibited in the interrupt sequences #3 and #4.

Sequence intervals

A sequence will start automatically after the selected interval time.

Sequence intervals (1023h - 103Fh)

Sequence

address

Interval in 10 ms

3

1023h

0, 1 - 255

up to

up to

0, 1 - 255

31

103Fh

0, 1 - 255

no sequence starts when interval = 0

Sequence start addresses

The following table defines the start addresses for each sequence.

Sequence start addresses (1040h - 107Fh)

Sequence

address

Start address

0

1040h

0xxxh

1

1042h

0xxxh

up to

up to

0xxxh

31

107Eh

0xxxh

no sequence starts when start address = 0000h

Sequence 0 starts automatically after power up or Node reset (hardware or reset node command),
Sequence 1 starts automatically after a start node command,
Sequence 2 starts automatically after a stop node command.

Sequences 0,1 and 2 cannot be started on an interval or reading/writing of user memory or a CALL command.

Sequence 3 and/or 4 can be called directly from the CAN controller interrupt. 
When the sequence is assembled in native code and all application layer settings conditions are met.

Sequence start on write

By writing a memory location by the application, e.g. a CANopen PDO write, a sequence can be started.
The sequence will be started after write to the memory location.

Sequence start on write (1080h - 10DFh)

User memory

address

Sequence

0

1080h

3 - 31

1

1081h

3 - 31

up to

up to

3 - 31

95

10DFh

3 - 31
no sequence starts when sequence = 0  
Sequence start on read

By reading memory location by the application, e.g. a CANopen PDO write, a sequence can be started.
The sequence will be started before a read from a memory location.

Sequence start on read (10E0h - 113Fh)

User memory

address

Sequence

0

10E0h

3 - 31

1

10E1h

3 - 31

up to

up to

3 - 31

95

113Fh

3 - 31

no sequence starts when sequence = 0

Starting a sequence by reading or writing memory is only valid via CAN bus accesses (e.g. SDO, PDO). Any internal access from within a sequencer program will not start another sequence.

 

Sequence command memory

Sequencer command memory (1140h - 4FFFh)

address

command

1140h

first command

1142h

2nd command

up to

more commands

4FFEh

last possible command

In emulated mode, a command always contains 2 bytes, the first byte (at even address) is the command, the 2nd byte contains additional data.

When writing the command table to memory, the 16 Kb FLASH memory is in fact completely erased first. So the user must send the complete table.
It is not necessary to send the complete 16 Kb, only the first 140h bytes are mandatory, the rest depends on the total sequencer program length.

Sequencer instructions

Symbolic Name (alias)

Code

Data

Description

Emulated mode execution time in µS (Note)

Valid Flags

Bytes in native code

Native Code execution time in µS (Note)

 D
I
S
Working Register

LDWM

00h

0 - 255

Load working register from memory

6.5

Z -

 2 - 3 0.4 - 0.6  

STWM

01h

0 - 255

Store working register to memory

6.5

Z -

 2 - 3 0.4 - 0.53  

LDWC

02h

0 - 255

Load working register with constant (immediate value, 0 - 255)

 5.9

Z -

 2 0.27  

ANDWC

03h

0 - 255

Bit wise logical AND working register with constant

 6.3

Z -

 2 0.27  

ORWC

04h

0 - 255

Bit wise logical OR working register with constant

 6.3

Z -

 2 0.27  

XORWC

05h

0 - 255

Bit wise logical XOR working register with constant

 6.3

Z -

 2 0.27  

SHLWC

06h

1 - 7

Shift working register 1 - 7 bits left, empty places filled with 0

 5.5+n*0.93

Z C

 1 - 5 0.13 - 0.67  

SHRWC

07h

1 - 7

Shift working register 1 - 7 bits right, empty places filled with 0

 5.5+n*0.93

Z C

 1 - 5 0.13 - 0.67  

ADDWC

08h

0 - 255

Add constant to working register

 6.3

Z C

 2 0.27  

SUBWC

09h

0 - 255

Subtract constant from working register

 6.7

Z C

 2 0.27  

ANDWM

0Ah

0 - 255

Bit wise logical AND working register with memory

 6.9

Z -

 2 - 3 0.4 - 0.53  

ORWM

0Bh

0 - 255

Bit wise logical OR working register with memory

 6.9

Z -

 2 - 3 0.4 - 0.53  

XORWM

0Ch

0 - 255

Bit wise logical XOR working register with memory

 6.9

Z -

 2 - 3 0.4 - 0.53  

ADDWM

0Dh

0 - 255

Add memory to working register

 6.9

Z C

 2 - 3 0.4 - 0.53  

SUBWM

0Eh

0 - 255

Subtract memory from working register

 6.9

Z C

 2 - 3 0.4 - 0.53  
SWAPWM 0Fh

0 - 255

 Swap working register with memory 7.5 - - 6 - 7 1.33  

CMPWC

18h

0 - 255

Compare working register with constant

 6.3

Z C

 2 0.27  

CMPWM

19h

0 - 255

Compare working register with memory location

 6.5

Z C

 2 - 3 0.4 - 0.53  

BITWC

1Ah

0 - 7

Test bit in working register, bit number 0 - 7

 6.5

Z -

 2 0.27  

ADCWC

1Ch

0 - 255

Add constant and Carry to working register

 6.8

Z C

 2 0.27  

ADCWM

1Dh

0 - 255

Add memory and Carry to working register

 7.5

Z C

 2 - 3 0.4 - 0.53  

SBCWC

1Eh

0 - 255

Subtract constant and Carry from working register

 7.6

Z C

 2 0.27  

SBCWM

1Fh

0 - 255

Subtract constant and Carry from working register

 7.5

Z C

 2 - 3 0.4 - 0.53  

LDWI

28h

0 - 255

Load working register indirect (memory location contains effective memory location)

 6.9

Z -

 3 - 5 0.67 - 0.93  

STWI

29h

0 - 255

Store working register indirect

 6.9

Z -

 2 - 5 0.53 - 0.93  

ROLWC

2Ah

1 - 7

Rotate working register 1 - 7 bits left, through Carry

 6.0+n*0.93

Z C

 1 - 4 0.13 - 0.53  

RORWC

2Bh

1 - 7

Rotate working register 1 - 7 bits right, through Carry

 6.0+n*0.93

Z C

 1 - 4 0.13 - 0.53  

RLCWC

2Ch

1 - 7

Rotate working register 1-7 bits left, circular

n=1
n=2
n>2

6.9
8.0
5.9+n*1.07

Z C

3
5
5

0.4
0.67
2.3+n*1.07		  

RRCWC

2Dh

1 - 7

Rotate working register 1-7 bits right, circular

n=1
n=2
n>2

6.9
8.0
5.9+n*1.07

Z C

3
5
5

0.4
0.67
2.3+n*1.07		  

LDWIO

2Eh

109

Load working register from RS232 receive buffer

16.5 -21.3

- -

 3 7.3 - 12.1 X

LDWIO

2Eh

110

Load working register with amount of received characters in RS232 receive buffer

11.2

- -

 3 2.1 X

LDWIO

2Eh

111

Load working register with amount of free space in RS232 transmit buffer

11.2

- -

 3 2.1 X

LDWIO

2Eh

112

Load working register from PWM frequency low

9.7

- -

 2 0.4 X

LDWIO

2Eh

113

Load working register from PWM frequency high

9.7

- -

 2 0.4 X

LDWIO

2Eh

114

Load working register from PWM duty cycle low

9.7

- -

 2 0.4 X

LDWIO

2Eh

115

Load working register from PWM duty cycle high

9.7

- -

 2 0.4 X

LDWIO

2Eh

118

Load working register from I2C bus (shift in a byte), standard / fast

101.7 /  42.9

 - - 3 93.3 / 34.5 X

LDWIO

2Eh

119

Load working register from SPI shift speed configuration

9.7

- -

 2 0.4 X

LDWIO

2Eh

120

Load working register from SPI shift pattern configuration

10.2

- -

 2 0.4 X

LDWIO

2Eh

121

Load working register with last in-shifted byte (during last shift in or last shift out....)

10.2

- -

 2 0.4  

LDWIO

2Eh

122

Load working register from SPI bus (shift in a byte)

Shift_Speed (memory location 119) = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3

 

14.5 - 15.3
20.5 - 22.0
46.5 - 52.0
149.2 - 167.3

 - -

 3

5.7 - 6.5
11.7 - 13.2
37.7 - 43.2
141.1 - 158.5		  

LDWIO

2Eh

123

Load working register from parallel output port A (latch)

10.7

- -

 2 - 3 0.4 - 2.4  

LDWIO

2Eh

124

Load working register from parallel output port B (latch)

10.7

- -

 3 2.7  

LDWIO

2Eh

125

Load working register from parallel input port C

14.0

- -

 3 5.7  

LDWIO

2Eh

126

Load working register from 8 bits analogue input 1

26.4 - 28.0

- -

 3 17.3 - 20.0 X

LDWIO

2Eh

127

Load working register from 8 bits analogue input 2

STWIO

2Fh

107

Store working register to RS232 configuration (or use the RSCFC instruction)

W = 0
W <> 0


11.7
21.0 - 25.0

- -

 3


3.0
12.4 - 16.4		 X

STWIO

2Fh

108

Store working register in RS232 transmit buffer

 16.3

- -

 3 7.7 X

STWIO

2Fh

112

Store working register to PWM frequency low

 9.1

- -

 2 0.4 X

STWIO

2Fh

113

Store working register to PWM frequency high

 9.1

- -

 2 0.4 X

STWIO

2Fh

114

Store working register to PWM duty cycle low

 9.1

- -

 2 0.4 X

STWIO

2Fh

115

Store working register to PWM duty cycle high

 18.5 - 22.9

- -

 5 10.8 - 15.2 X

STWIO

2Fh

116

Storing to MISC makes no sense because special sequencer instructions exist to do this (I2STP, I2STA, I2STP, SYNC, CRDY, SRDY)

W = 0
W = 1
W = 2
W = 3
W = 4
W = 5
W = 6
W = 7

  

 

- -		     X

STWIO

2Fh

117

Store working register to I2C bus (shift out a byte), standard / fast

 100.5 / 43.0

- -

 3 92.3 / 32.8 X

STWIO

2Fh

119

Store working register to SPI shift speed configuration

 12.8

- -

 5 5.1 X

STWIO

2Fh

120

Store working register to SPI shift pattern configuration

 12.8

- -

 5 5.1 X

STWIO

2Fh

121

Store working register to SPI bus (shift out a byte)

Shift_Speed (I/O location 119, bit 1,0 = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3

13.4 - 14.3
19.5 - 20.9
45.5 - 50.9
148.1 - 166.3

- -

 3

5.7 - 6.5
11.7 - 13.2
37.7 - 43.2
141.1 - 158.5		  

STWIO

2Fh

123

Store working register to parallel output port A

 10.8

- -

 2 - 3 0.4 - 4.1  

STWIO

2Fh

124

Store working register to parallel output port B

 11.1

- -

 3 4.4  
LDWE 68h

0 - 63

 Load working register from EEPROM memory 7.3 - 11mS - - 5 4.3 - 11mS  
STWE 69h

0 - 63

 Store working register to EEPROM memory 25 - 22mS - - 5 25 - 22mS  
LDWEI 6Eh

0 - 255

 Load working register from EEPROM memory indirect 8.7 - 11mS - - 5 - 6 4.3 - 11mS  
STWEI 6Fh

0 - 255

 Store working register to EEPROM memory indirect 25 - 22mS - - 5 - 6 25 - 22mS  

TABLE

55h

0 - 255

 Set internal table pointer to selected table and return table length in working register 9.3 Z - 5 5.1  
LDWT 56h

0 - 255

 Load working register from table, index in operand 7.7 Z - 4 0.9  
LDWTI 57h

0 - 255

 Load working register from table, index in memory location 8.4 Z - 6 4.0  
Memory

SHLM

48h

0 - 255

Shift memory location left one bit, shift a zero into bit 0, bit 7 into Carry

 6.4

Z C

 2 - 5 0.53 - 0.93  

SHRM

49h

0 - 255

Shift memory location right one bit, shift a zero into bit 7, bit 0 into Carry

 6.4

Z C

 2 - 5 0.53 - 0.93  

ROLM

4Ah

0 - 255

Rotate memory location left one bit, shift Carry into bit 0, bit 7 into Carry

 6.9

Z C

 2 - 5 0.53 - 0.93  

RORM

4Bh

0 - 255

Rotate memory location right one bit, shift Carry into bit 7, bit 0 into Carry

 6.9

Z C

 2 - 5 0.53 - 0.93  

DECM

4Ch

0 - 255

Decrement memory location

 6.4

Z -

 2 - 5 0.53 - 0.93  

INCM

4Dh

0 - 255

Increment memory location

 6.4

Z -

 2 - 5 0.53 - 0.93  

TESTM

4Eh

0 - 255

Test memory location (zero/nonzero)

 6.3

Z -

 2 - 5 0.53 - 0.93  

CLRM

4Fh

0 - 255

Clear memory location

 5.7

- -

 2 - 5 0.53 - 0.93  

BIT0M

58h

0 - 255

Test memory location's bit 0, result in Z flag

 6.5

Z -

 4 - 7 0.67 - 1.33  

BIT1M

59h

0 - 255

Test memory location's bit 1, result in Z flag

 6.5

Z -

 4 - 7 0.67 - 1.33  

BIT2M

5Ah

0 - 255

Test memory location's bit 2, result in Z flag

 6.5

Z -

 4 - 7 0.67 - 1.33  

BIT3M

5Bh

0 - 255

Test memory location's bit 3, result in Z flag

 6.5

Z -

 4 - 7 0.67 - 1.33  

BIT4M

5Ch

0 - 255

Test memory location's bit 4, result in Z flag

 6.5

Z -

 4 - 7 0.67 - 1.33  

BIT5M

5Dh

0 - 255

Test memory location's bit 5, result in Z flag

 6.5

Z -

 4 - 7 0.67 - 1.33  

BIT6M

5Eh

0 - 255

Test memory location's bit 6, result in Z flag

 6.5

Z -

 4 - 7 0.67 - 1.33  

BIT7M

5Fh

0 - 255

Test memory location's bit 7, result in Z flag

 6.5

Z -

 4 - 7 0.67 - 1.33  
Output Port A

OUTA

10h

0 - 255

Output user memory location to parallel output port A

 8.1

- -

 4 - 6 0.8 - 4.7  

SETA

11h

0 - 7

Set bit in parallel output port A, bit number 0 - 7

 6.8

- -

 2 - 5 0.53 - 3.1  

RESA

12h

0 - 7

Reset bit in parallel output port A

 6.9

- -

 2 - 5 0.53 - 3.2  

TGLA

13h

0 - 7

Toggle bit in parallel output port A

 6.8

- -

 2 - 5 0.53 - 3.1  

MASKA

14h

0 - 255

Set port A masking (the bits allowed to change, NOTE)

 5.3

- -

 3 0.53  

BITA

15h

0 - 7

Test bit in parallel output port A, bit number 0 - 7 (bit always reads as zero if MASKA is zero for that bit)

 6.9

Z -

 4 - 5 0.67 - 2.7  

OUTAC

16h

0 - 255

Output constant to output port A

 7.5

- -

 3 - 5 0.53 - 4.4  
Output Port B

OUTB

20h

0 - 255

Output user memory location to parallel output port B

 8.4

- -

 5 - 6 4.8 - 4.9  

SETB

21h

0 - 3

Set bit in parallel output port B

 6.8

- -

 2 - 5 0.53 - 3.1  

RESB

22h

0 - 3

Reset bit in parallel output port B

 6.9

- -

 2 - 5 0.53 - 3.2  

TGLB

23h

0 - 3

Toggle bit in parallel output port B

 6.8

- -

 2 - 5 0.53 - 3.1  

MASKB

24h

0 - 15

Set port B masking (the bits allowed to change, NOTE)

 5.3

- -

 3 0.53  

BITB

25h

0 - 3

Test bit in parallel output port B, bit number 0 - 3 (bit always reads as zero if MASKB is zero for that bit)

 6.9

Z -

 4 - 5 0.67 - 2.7  

OUTBC

26h

0 - 255

Output constant to output port B

 7.7

- -

 5 4.7  
Input Port C

INPC

30h

0 - 255

 Input parallel input port C to user memory location 10.1

- -

 5 - 6 6.1 - 6.3  
SEQCE  31h dd Activate a sequence on a port C (0 - 3 = in1 - in4) input edge
Bit Description
0 - 1 port bit number (0 - 3)
2 sets rising (1) or falling (0) edge
3 - 7 selects the sequence to start (3 - 31), no sequence when 0
9.6

- -

 5 6.5 X
SEQCL 32h

dd

 Activate a sequence on a port C (4 - 7 = in5 - in8) input level
Bit Description
0 - 1 port bit number (0 - 3 = bit 4 - 7)
2 sets high level (1) or low (0) level
3 - 7 selects the sequence to start (3 - 31), no sequence when 0
7.5 - - 5 4.4 X

MASKC

34h

0 - 255

 Set port C masking (the bits allowed to read, NOTE) 5.3

- -

 3 0.53  

BITC

35h

0 - 7

 Test bit in parallel input port C, bit number 0 - 7 (bit always reads as zero if MASKC is zero for that bit) 10.3

Z -

 4 - 5 0.67 - 6.0  
Branch

BRA

40h

rel

Program branch : rel = -128 .... 127
1 - 128 instructions backward
0 - 127 instructions forward
BRA 0 branches to next command

 7.2

- -

 2 - 5 0.4 - 0.8  

BEQ

41h

rel

Program branch when the zero flag is one

 5.6 - 8.3

- -

 2 - 5 0.4 - 0.8  

BNE

42h

rel

Program branch when the zero flag is zero

 5.6 - 8.3

- -

 2 - 5 0.4 - 0.8  

BCS (BLO)

43h

rel

Program branch when the carry flag is one

 5.6 - 8.3

- -

 2 - 5 0.4 - 0.8  

BCC (BHS)

44h

rel

Program branch when the carry flag is zero

 5.6 - 8.3

- -

 2 - 5 0.4 - 0.8  

BCANE

45h

rel

Program branch when Application Layer can send a CAN message

 7.5 - 10.1

- -

 5 - 8 2.5 - 2.9  

BCANF

46h

rel

Program branch when Application Layer can NOT send a CAN message

 7.5 - 10.1

- -

 5 - 8 2.5 - 2.9  

Serial Bus

SHOM

50h

0 - 255

Shift-out user memory location via the SPI shifter

Shift_Speed (memory location 119) = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3



10.9 - 11.7
16.9 - 18.4
42.9 - 48.4
145.6 - 163.7

- -

 5 - 6

6.1 - 7.1
12.1 - 13.7
38.1 - 43.7
140.8 - 159.1		  

SHIM

51h

0 - 255

Shift-in user memory location via the SPI shifter

Shift_Speed (memory location 119) = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3

11.5 - 12.3
17.5 - 18.9
43.5 - 48.9
146.1 - 164.3

- -

 5 - 6

6.1 - 7.1
12.1 - 13.7
38.1 - 43.7
140.8 - 159.1		  

SHSPD

52h

0 - 3

Set SPI shifter shift speed (data is same as I/O location 119)

 10.1

- -

 6 5.7 X

SHPAT

53h

0 - 7

Set SPI shifter shift pattern (data is same as I/O location 120)

 10.1

- -

 6 5.7 X

SHOC

54h 

0 - 255

Shift out constant via the SPI shifter

Shift_Speed (memory location 119) = 0
Shift_Speed = 1
Shift_Speed = 2
Shift_Speed = 3

9.7 - 10.5
15.7 - 17.2
41.7 - 47.2
144.4 - 153.7

- -

 5

6.0 - 6.8
12.0 - 13.5
38.0 - 43.5
140.7 - 158.8		  
I2C Interface

I2OM

60h

0 - 255

Shift-out user memory location via the I2C bus, standard / fast

 97.6 / 38.1

- -

 5 - 6 92.8 / 33.3 X

I2IM

61h

0 - 255

Shift-in a byte from the I2C bus to the user memory location

 99.1 / 40.3

- -

 5 - 6 93.8 / 35.1 X

I2STP

62h

0

Output a STOP condition on the I2C bus

 17.7 / 9.6

- -

 3 14.2 / 6.1 X

I2STA

63h

0

Output a START condition on the I2C bus

 27.3 / 11.5

- -

 3 23.9 / 8.0 X

I2LST

64h

0

Indicates that the next read command will be the last, and should not be acknowledged

 5.5

- -

 2 0.53 X

I2OC

65h

0 - 255

Shift-out constant via the I2C bus

 96.3 / 36.8

- -

 5 92.1 / 32.7 X

I2SPD

66h

0 - 1

 0: sets standard (100 kbps) I2C speed
1: sets fast (330 kbps) I2C speed		 6.0   2 0.53 X
RS232 Interface

RSOM

6Ah

0 - 255

Shift-out memory location to RS232 interface (buffer)

 12.4

- -

 5 - 6 8.1 - 8.3 X

RSIM

6Bh

0 - 255

Shift-in memory location from RS232 interface (buffer)

 13.1 - 17.9

- -

 5 - 6 7.7 - 12.7 X

RSCFC

6Ch

0

dd

Configure RS232, zero means that sequencer releases the RS232.
Format as with writing to the RSCFG memory location

 16.4 - 20.4

- -

 5 12.3 - 16.3 X

RSOC

6Dh

0 - 255

Shift-out constant value via RS232 interface

 11.7

- -

 5 7.6 X
Miscellaneous  

DELAY

70h

n

Delay, n times 2 µS (n=1-255)

 4.9 + n*2

- -

 5 1.9 + n*2  

SYNC

71h

0,1,2

0: Outputs a 2 uS high pulse on the SYNC output
1: Disable CAN generated SYNC pulse
2: Enable CAN generated SYNC pulse

 8.0
6.5
6.5

- -

 5 4.9
3.5
3.5		  

CRDY

72h

0

Clears READY output (low, out1 .. out12 are tri-stated)

 5.5

- -

 2 0.53  

SRDY

73h

0

Sets READY output (high, out1 .. out12 are activated)

 5.5

- -

 2 0.53  

CALL

74h

3 - 27

Subroutine call of another sequence, even if it is disabled.
Sequences 0-2 and 28-31 can not be called.

 9.6

- -

 3 0.67  

ERROR

75h

1 - 8

Notify an error to the application layer (like CANopen)

 6.4

- -

 2 0.53  

ERROF

76h

1 - 8

Notify end of error to the application layer

 6.4

- -

 2 0.53  

CANSND

77h

10h-18h
20h-28h

 Send CAN message with 1-8 byte data from memory location 0-7, transmission only starts when all conditions for CANSND command are satisfied. 33.1 - - 3 29.6  
FSTINT 78h 0 - 1 0: disable fast sequence interrupt (sequence #3/#4)
1: enable fast sequence interrupt (sequence #3/#4)
This command is only operative in native mode.
Using FSTINT 1 for the first time will activate fast sequence interrupts, but all application layer conditions have to be met.
After re-enabling FSTINT, any pending interrupt sequences will  be serviced immediately.		  - - - 2 - 3 0.53 - 2.9  

ENASQ

7Bh

0,1-31